Presented at IWOCL and SYCLcon 2021
Today, system-on-chip manufacturers are building specialist accelerator processors based on the RISC-V architecture, taking advantage of the Vectorized (RVV) extensions that match compute performance mostly seen on GPUs today. The availability of a familiar and well defined programming model is an absolute requirement if expecting to successfully bring these new processors to market.
This presentation will describe the components needed to integrate OpenCL and SYCL onto RISC-V Vector solution using multiple simulators. While Codeplay has previously enabled OpenCL for a variety of processor architectures, there are a number of technical challenges involved in delivering a generic integration that can be rapidly used by multiple RVV based systems, a solution that requires a change in development approach. By adding to the existing LLVM back-end for RISC-V, and creating an integration layer that plugs into OpenCL, we have built a common base architecture for a variety of RISC-V processors.
This presentation will explain how Codeplay’s current driver interface works, and how it has been adapted to integrate with multiple RISC-V targets, in particular the Spike RISC-V ISA simulator. We will also talk about some of the RISC-V Vector extensions that are available, and how these can help to expose features specific to the RISC-V architecture through OpenCL.
RISC-V is a non-profit, member managed organization and is gaining momentum in the processor space, with more than 900 members. One of the goals of the organization is to build an open software platform, providing software developers an easy way to harness the familiar benefits already available on CPUs and GPUs