Events

Events

Montreal International Games Summit

Codeplay is pleased to announce that CEO Andrew Richards has been confirmed as a speaker at the Montreal International Games Summit on November 8-9.

Andrew will be taking a detailed look at the requirements in designing a multi-core game engine that will be future-proof against future generations of games hardware.

Designing a game engine that gives excellent performance across the different processing architectures of the PC, PlayStation3 and XBox 360 is hard. Ensuring a game engine isn't obsolete when future processing technologies like CUDA and OpenCL arrive is even harder. This talk discusses different ways of creating game engines that can scale to large numbers of cores in a way that is portable, easy to debug, easy to develop for, and scales to future architectures. There are a variety of different kinds of parallelism available: pipeline parallelism, task-farm and data-parallel. There are also a variety of memory architectures available. Each of these solutions is suitable for different situations, so programmers need to have a toolbox of options available at all times and understand the performance implications. Debugging and analysing parallel applications is hard, so techniques for ensuring engines provide good debug and analysis features will be presented. Game developers need to be able to deep dive into parallel systems to be able to find and fix problems quickly, so solutions that enable developers to modify any part of the system for their own needs will be presented. This might involve domain-specific languages, or C++ template meta-programming. Learning objectives • Steps to designing a portable, future-proof game engine. • Understanding different types of parallelism and achieving best performance. • Analysis and debugging in a parallel environment.

The full schedule of talks taking place at MIGS can be found here.

Codeplay to present at PHDRS2010 at the University of Glasgow

Dr George Russell, Director of Quality Assurance at Codeplay, will be giving a presentation at the 2nd Workshop on Programming and Design of Heterogeneous and Reconfigurable Systems (PDHRS).

PDHRS2010 will be held 4-5th of August at the University of Glasgow. Dr Russell will be speaking on Thursday at 10:15 and will cover Programming Heterogeneous Multicore Systems using Threading Building Blocks.

Intel’s Threading Building Blocks (TBB) provide a high-level abstraction which allows programmers to express parallelism in their applications without having to write multithreaded code. However, TBB is only available for shared memory, homogeneous multicore processors. Codeplay’s Ofﬂoad C++ provides a single-source, POSIX threads-like approach to programming heterogeneous multicore devices where cores are equipped with private, local memories - code to move data between memory spaces is generated automatically. In this paper, we show that the strengths of TBB and Ofﬂoad C++ can be combined, by implementing part of the TBB headers in Ofﬂoad C++. This allows applications written using TBB to run, without source-level modiﬁcations, across the PPE and SPE cores of the Cell BE processor. We present experimental results applying our method to a set of TBB programs. To our knowledge, this work marks the ﬁrst demonstration of TBB for a heterogeneous multicore architecture.

Also on the multicore programming tract, Oxford University's Dr Alastair Donaldson, Scientific Advisor to Codeplay, will be talking about Automatic Analysis of Scratch-Pad Memory Code for Heterogeneous Multicore Processors

Modern multicore processors, such as Cell, achieve high performance by equipping accelerator cores with scratch-pad. This comes at the expense of programming complexity – the programmer must manually orchestrate data movement using error-prone direct memory access (DMA) operations. We show how formal verification techniques based on Bounded Model Checking and k-induction can be used to detect or prove absence of DMA races in multicore software.

Dr Donaldson will be presenting at 9.30 on Thursday.

One more Codeplay affiliated speaker will also be presenting. EPSRC CASE Industrial Ph.D. Research Student Paul Keir continues the theme with A Parallel Array Compiler for the Cell Broadband Engine.

Heterogeneous multicore systems are increasingly applied to scientific computing. However, good performance expects optimised temporal and spatial data locality. Array languages encourage users to engineer using elements which are inherently divisible, and often parallelisable. This talk will describe extensions to a Fortran array language, and their implementation within a new CellBE compiler.

Paul's presentation begins at 12, making for a very engaging morning for multicore software developers.

Codeplay Technical Paper Accepted for Euro-Par

A technical white paper written by Codeplay staff and close associates has been accepted for the Euro-Par conference. Euro-Par 2010 will be held in Naples, Italy from August 21st to September 3rd. Euro-Par is an annual series of international conferences dedicated to the promotion and advancement of all aspects of parallel computing and distributing computing.

Codeplay's paper is titled "Programming Heterogeneous Multicore Systems using Threading Building Blocks".

Intel’s Threading Building Blocks (TBB) provide a high-level abstraction for expressing parallelism in applications without writing explicitly multithreaded code. However, TBB is only available for shared-memory, homogeneous multicore processors. Codeplay’s Offload C++ provides a single-source, POSIX threads-like approach to programming heterogeneous multicore devices where cores are equipped with private, local memories—code to move data between memory spaces is generated automatically. In this paper, we show that the strengths of TBB and Offload C++ can be combined, by implementing part of the TBB headers in Offload C++. This allows applications parallelised using TBB to run, without source-level modifications, across all the cores of the Cell BE processor. We present experimental results applying our method to a set of TBB programs. To our knowledge, this work marks the first demonstration of programs parallelised using TBB executing on a heterogeneous multicore architecture.

Codeplay at Hot Chips 2010

Delegates from Codeplay Software will be attending Hot Chips 22, one of the semiconductor industry's leading conferences on high-performance microprocessors.

The event takes place August 22-24 at Memorial Auditorium, Stanford University, Palo Alto.

If you'd like to meet with Codeplay for an informal discussion while we are in the Silicon Valley area or at Hot Chips itself then email This e-mail address is being protected from spambots. You need JavaScript enabled to view it to set up an appointment.

We look forward to seeing you there.

Codeplay at International Supercomputing Conference

Codeplay is looking forward to participating in the International Supercomputing Conference 2010 in Hamburg, Germany next week. The event is Europe's leading conference on High Performance Computing.

Andrew Richards, CEO and Chief Systems Architect of Codeplay, will be giving a talk "Writing High-Performance Multicore-Optimized Programs on the Cell Broadband Engine™ with Offload™".

The era of multi-core heralds new low-cost, low-power heterogeneous multicore hardware, such as the Cell Broadband Engine™, that provide cost competitive building blocks for HPC systems. However, Cell’s unusual architecture can cause uncertainty when trying to write programs that obtain the best performance advantage from the hardware.

Codeplay’s Offload™ is a full SDK and programming model for writing optimized applications for the Cell Broadband Engine™. The principles behind the Offload™ programming model are based on the need to have a multi-core programming system that delivers best performance for complex real-world applications. Unlike many other multi-core tools, Offload™ does not focus on parallelizing software. Instead, Offload™ focuses on providing a migration path from host PPE to SPE. Heterogeneous multi-core eliminates the problem of memory bandwidth saturation that occurs with Symmetric Multi-Threading multi-core processors by requiring software developers to handle memory accesses themselves, by using separate local and shared memories, or streaming DMA. Offload™ lets programmers take full advantage of the memory-bandwidth features of heterogeneous multi-core, but only requiring minimal and incremental changes to source code.

The talk aims tol provide an overview of Offload™ and with some real examples, illustrate why it is a good choice for heterogeneous multicore programming. The talk will be given on 1st June at 12:40PM - 01:00PM in Hall H, #001.

See the full conference agenda here.

You can also visit Codeplay at booth 300-4.

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